The present invention relates to the field of Silicon-On-Insulator (SOI) Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) circuitry. In particular, the present invention involves ratioed logic with intrinsically ON symmetric double-gate (DG) SOI MOSFET loads.
Over the last few years, researchers have investigated DG SOI MOSFET designs as enabling Silicon (Si) devices for the 0.05 μm node and beyond. As a result, a number of DG structures have been proposed and analyzed. Many of these structures have been categorized as symmetric (SDG), where both gates are made of the same polysilicon type (usually n+), and asymmetric (ADG), where one gate is n+ and the other gate is p+ type polysilicon. The n+ gate SDG is usually a “normally on” device having a negative threshold voltage. Therefore, one may need to use exotic gate materials (such as metal gates with appropriate work function values), which may require expensive and complicated processing steps.
Referring to FIG. 1, we see an example of such a basic Double Gate (DG) structure. As illustrated, one can see basic elements of the structure including: a source, drain, front gate, and back gate. The channel length is shown as LG. Different node voltages shown include: front gate voltage 201; drain voltage 202; source voltage 203, and back gate voltage 204. Also illustrated are several thicknesses, including silicon thickness (tSi) 205, front gate oxide thickness (toxf) 206, and back gate oxide thickness (toxb) 207. Designs using SDG gates often require fine-tuning an SDG gate using expensive and complicated processing techniques. For this and other reasons, designs implementing ADG devices have been favored.
FIG. 2 shows a basic Pseudo-nMOS logic design, in which both PMOS and NMOS transistors are combined to produce logic elements. In this exemplary inverter design, PMOS gate 102 is tied to ground 107 and has its source tied to VDD 101. NMOS gate 103 is tied to input 104, and its source is tied to GND 107. The junction of PMOS 102 drain and NMOS 103 source forms the output 105. CL 106 is the load capacitance. Pseudo-nMOSFET or ratioed logic designs have been known to be fast and small and offer small parasitic capacitance (hence a smaller load). The main drawback of these pseudo-nMOS designs have been their consumption of high static power. [See Jan. M. Rabaey, “Digital Integrated Circuit: A Design Perspective,” Prentice Hall, 1996; D. Radhakrishnan, “Design of CMOS Circuits,” IEEE Proceedings-G, Vol 138, No. 1, p 83, February 1991.] With the advent of CMOS logic and the growing need for lower power circuits, pseudo-nMOS/ratioed design style fell out of favor with designers and are starting to be seen only in critical path elements where speed and area are at a premium. [See N. H. E. Weste and K. Esraghian, “Principles of CMOS VLSI Design,” Addison Wesley, 1993.] Now, as SOI is becoming the base of mainstream technology, design constraints are changing. SOI may offer low junction capacitance. Demonstrations have shown that pseudo-nMOS/ratioed logic on SOI technology may offer significant performance and area improvements. Thus, pseudo-nMOS/ratioed logic on SOI may be used widely in SOI custom-integrated circuits.
As the search for smaller and faster circuits is growing, the much-needed continuous thrust for device scaling in meeting performance and power consumption criteria in Ultra Large Scale Integration (ULSI) circuits is pushing the conventional bulk CMOS technology towards its fundamental physical limits. As device dimensions shrink to submicron and below, limitations of bulk CMOS technology are becoming more pronounced due to strong short-channel effect (SCE) and possible quantum phenomenon, causing performance limitations and degradation. Because of their near-ideal intrinsic features, DG fully depleted SOI MOSFETs may be a better technology choice for the cutting edge nano-scale circuits. In addition to its inherent robustness to the SCEs and naturally steep subthreshold slope, DG MOSFETs may also be capable of offering higher drive current and transconductance. These devices are vigorously researched and evolving. Most structures commonly categorized as symmetric (SDG) have both gates made of the same polysilicon type (usually n+). Most structures commonly categorized as asymmetric (ADG) have one n+ gate and p+ type polysilicon gate.
Despite so much interest in DG SOI devices, there are few reports on circuit applications using these devices. There are reports that discuss the circuits use of DG SOI devices, but those are based on a straightforward mapping of bulk devices or using the CMOS blocks. CMOS-based logics are not good when considering dynamic power dissipation problems, which are prominent factors compared to static power at high frequency operation. CMOS-based logic also suffer from the larger number (2n) of devices problem.
What is needed is a new DG SOI gate construction that has speed and power advantages over regular CMOS gates. Preferably, this new gate construction will be a flexible building block capable of being used to construct a set of basic logic operations with a minimal number of devices.